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Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 8-13
System Reset
8.3.1 ICH4: PWROK
This pin causes the ICH4 to assert PCIRST#. It may be connected to PWRGOOD pins of all E8870
chipset components (as illustrated in Figure 8-7), or the result of an OR of PWRGOOD, SNC
RESETO# pins, or other sources of hard reset (as illustrated by Figure 8-8). PWROK must be
delayed until SIOH clocks to the ICH4 are stable.
8.3.2 Basic Reset Distribution
Figure 8-8 shows an example on the reset distribution of an E8870 chipset system. The ICH4 will
generate PCIRST# from either PWRGOOD or writes to certain registers. This PCIRST# will be
buffered and distributed to each component’s RESETI#. The SIOH generates RESET66# on each
Hub Interface, and the SNC generates RESET# to processors, MEMRST#, and LRESET#.
8.3.3 SIOH: DET
The DET pin is strapped high to enable determinism in the E8870 chipset. If high, CLK33 and
CLK66 references are reset on first hard reset deassertion as described in Section 8.2.2.4, “Hard
Reset Deassertion Sequence”. If this pin is low, the dividers that provide references for these clocks
can come up at an arbitrary phase relative to the same clocks on other SIOHs and SNC memory
maintenance operations.
8.3.4 ICH4: PCIRST#
ICH4 will drive PCIRST# for a minimum of 1ms after the deassertion of its PWROK pin or when the
hard reset sequence is initiated through the CF9 I/O register. For non-deterministic systems, this may
be connected to RESETI# of the SNC, SIOH, and SPS.
Figure 8-7. Simplest Power Good Distribution
SPSs SNCs
Processors
SIOHs
ICH4s
Power Good
Logic
DMHs
PWRGOODPWRGOODPWRGOODPWRGOOD
PWRGOOD
PWROK
DET
- (SNC) Datasheet 1
- Contents 3
- Introduction 1 11
- Introduction 12
- Figure 1-1. Typical Itanium 12
- 2-Based Server Configuration 12
- 1.3 Architectural Overview 13
- 1.4 Interfaces 14
- 1.4.5 JTAG Interface 15
- 1.5 Terminology 16
- 1.6 References 18
- 1.7 Revision History 18
- Signal Description 2 19
- 2.2 SNC Signal List 20
- Signal Description 21
- Configuration Registers 3 31
- 3.2.3 BOFLA: Boot Flag Alias 32
- 3.3 SNC I/O Space Registers 33
- 3.5 PCI Standard Registers 34
- Configuration Registers 35
- 3.6 Address Mapping Registers 37
- 3-8 Intel 38
- • A[43:26] == BASE 40
- : 5C - 5Fh 41
- 3-12 Intel 42
- 3-14 Intel 44
- 3-18 Intel 48
- Table 3-6. DDR IOP Decodes 51
- 3-22 Intel 52
- 3.8.1 SYRE: System Reset 53
- 3-24 Intel 54
- 44h (Continued) 55
- 3.8.4 SPAD: Scratch Pad 56
- 3.8.6 BOFL: Boot Flag 57
- 3.9 Error Registers 63
- 3.9.4 ERRMASK: ERRST MASK 68
- Processor Bus 69
- : 40h(31:0), 44h(63:32) 71
- : 48h(31:0), 4Ch(63:32) 71
- 3-42 Intel 72
- : E0h(31:0), E4h(63:32) 73
- 3-44 Intel 74
- 3.10.2 PTCTL: Timer Control 76
- 3-48 Intel 78
- Response 79
- Events LO 82
- Events HI 83
- Resource Events 84
- : E8h (SPPMD0), F8h (SPPMD1) 87
- : E4h (SPPMC0), F4h (SPPMC1) 87
- 3-60 Intel 90
- 3.10.18 HPDATA: Hot Page Data 93
- 3-64 Intel 94
- System Address Map 4 97
- 4.1.1 Compatibility Region 98
- 4.1.1.1 DOS Region 98
- 4.1.1.2 VGA Memory Range 98
- 4.1.1.3 MDA Memory Range 98
- 4.1.1.4 C and D Segments 98
- 4.1.2 System Region 99
- 4.1.2.1 Local Firmware Range 99
- 4-4 Intel 100
- System Address Map 102
- Local Firmware Disabled 102
- 4.1.5 Main Memory Region 104
- 4.1.5.3.3 Node Interleaving 105
- 4.1.5.3.4 Limitations 105
- 4-10 Intel 106
- 4.2.1.2 SPS Registers 108
- 4.2.1.1 SNC Registers 108
- 4.2.1.3 SIOH Registers 109
- 4-14 Intel 110
- Table 4-7. Intel 112
- 4.3 I/O Address Map 114
- 4.3.2 Outbound I/O Access 115
- 4.3.2.1 Outbound I/Os 115
- 4.4 Configuration Space 116
- 4.5 Illegal Addresses 117
- Memory Subsystem 5 119
- 5.1.2 Reads 120
- 5.1.3 Writes 121
- 5.2 Error Correction 122
- 5.2.3 Software Scrubs 123
- Memory Subsystem 124
- 5.2.5.1 FRU Isolation 126
- 5.2.6 Memory Test 126
- 5.3 DDR Organization 127
- 5.3.2 DDR Features Supported 128
- 5-12 Intel 130
- 5.3.3 Power Management 132
- Serviceability 6 135
- Table 6-1. Intel 136
- E8870 Chipset Errors 136
- • Memory: 139
- • Configuration Registers: 139
- 6.1.2 Data Poisoning 140
- 6.1.3 Error Reporting 140
- 6.1.4 Interface Details 141
- 6.1.5 Time-Out 142
- Responsibilities 143
- 6.2.2 Server Management (SM) 144
- 6.2.3 OS/System Software 144
- 6.2.4 Device Driver 144
- 6.3 Availability 145
- 6.4 Hot-Plug 146
- 6.5 Chipset Error Record 147
- 6-14 Intel 148
- • Non-continuable (NC) 149
- • Continuable Single (CS) 149
- • Continuable Trailing (CT) 149
- 6-16 Intel 150
- 6-18 Intel 152
- 6.5.4 ESP Error Logs 154
- 6-22 Intel 156
- Clocking 7 157
- Clocking 158
- 7-4 Intel 160
- 7.8 JTAG 161
- 7.9 SMBus Clocking 161
- 7.11 Analog Power Supply Pins 161
- System Reset 8 163
- 8.2 Reset Sequences 164
- 8.2.1 Power-up Reset Sequence 165
- System Reset 166
- 8.2.1.1 PWRGOOD Deassertion 167
- 8-6 Intel 168
- 8.2.2 Hard Reset 169
- 8-8 Intel 170
- Incomplete 171
- Initialization 171
- Complete Initialization 171
- 50 System Clocks 171
- 8-10 Intel 172
- 8.2.2.7 Local Resets 173
- 8.3 Reset Signals 174
- 8.3.1 ICH4: PWROK 175
- 8.3.3 SIOH: DET 175
- 8.3.4 ICH4: PCIRST# 175
- 8-16 Intel 178
- Electrical Specifications 9 179
- 9.3.1 Overview 180
- 9.3.2 Signal Group 181
- 9.3.3 DC Specifications 182
- 9.5 Main Channel Interface 183
- 9.5.2 DC Specifications 184
- 9.5.3 AC Specifications 184
- 9.6 LPC Signal Group 185
- 9.7.1 DC Specifications 186
- 9.7.2 AC Specifications 187
- 9.7.3 AC Timing Waveforms 188
- 9.8.1 Signal Groups 189
- 9.8.2 DC Characteristics 190
- 9.8.3 AC Specification 191
- Electrical Specifications 192
- 9.9 Clock Signal Groups 193
- 9-16 Intel 194
- 10-2 Intel 196
- 10.2 Ball-out Specifications 197
- Table 10-1. SNC Ball List 198
- 10-6 Intel 200
- 10-8 Intel 202
- 10-10 Intel 204
- 10-12 Intel 206
- 10-14 Intel 208
- 10-16 Intel 210
- 10-18 Intel 212
- 10-20 Intel 214
- 10-22 Intel 216
- 10-24 Intel 218
- 10-26 Intel 220
- 10-28 Intel 222
- 10-30 Intel 224
- 10-32 Intel 226
- 10-34 Intel 228
- 10-36 Intel 230
- 10-38 Intel 232
- Testability 11 233
- 11.2 Public TAP Instructions 236
- 11.4 TAP registers 237
- 11-6 Intel 238
- Testability 239
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